1. Field of the Invention
This invention relates generally to a semiconductor memory device and, more particularly, to a Dynamic Random Access Memory (DRAM) cell having a trench storage capacitor wherein the retention time of the cell is significantly increased and leakage currents are eliminated by utilizing a buried oxide collar surrounding the trench.
2. Description of the Prior Art
There are many DRAM applications where it is important to maximize the retention time of the cell. In particular, applications depending on battery power for the system would benefit from a DRAM cell which did not need to be refreshed very often. Very Large Scale Integrated (VLSI) DRAM cells in the time frame of 4Mbit and beyond require trench storage capacitors in order to meet high density requirements. DRAM cells having a storage capacitor disposed in a trench formed in a semiconductor substrate are known in the art. For example, U.S. Pat. No. 4,688,063 assigned to the same assignee as the present invention, which patent is hereby incorporated by reference, discloses a substrate plate trench (SPT) DRAM cell which utilizes a trench storage capacitor formed in a semiconductor substrate. A portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench forms the other electrode of the storage capacitor. The SPT DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The trench capacitor extends from the surface of the well, through the well and lightly doped substrate portion, into the heavily doped portion of the substrate. The capacitor electrode disposed in the trench is directly connected to the source/drain of the access transistor.
In the SPT DRAM cell of U.S. Pat. No. 4,688,063, charge is stored on the dielectrically isolated polysilicon electrode formed within the trench in order to meet rigid leakage requirements. To further reduce leakage, the DRAM cell includes an n-well interposed between the substrate plate and the access transistor electrodes. As described in Cottrell et al., "N-Well Design for Trench DRAM Arrays", IEDM Tech. Digest, pp. 584-587, 1988, to further increase the immunity of an SPT DRAM cell to leakage current an n-well with a doping profile that monotonically decreases with depth can be utilized.
While leakage is significantly reduced in prior art SPT DRAM cells, a parasitic voltage dependent upon junction leakage current may inherently develop in the memory devices which limit the retention time of the cell. This leakage current is the result of two main leakage mechanisms, (1) generation of charge carriers in the space charge region of the trench electrode diffusion and (2) thermal generation of charge carriers along the depleted sidewall of the trench. The second mechanism is aggravated by the n-well which sets up an electric field that causes the generated carriers to be collected by the trench electrode diffusion. As described in Noble et al., "Parasitic Leakage in DRAM Trench Storage Capacitor Vertical Gated Diodes", IEDM Tech. Digest, pp. 340-343, 1987, another disadvantage of the SPT DRAM cell is that when a bias is applied to the trench, the gating action of the trench also affects the n-well/substrate junction which leads to an excess current from the n-well to the substrate. Thus, there is a need to develop an SPT DRAM cell which minimizes the inherent junction leakage current.